作者：李国梁1, 韩斌1, 程阳1,2, 曹杰1,2, 鲍春1, 吴昊泽1
作者单位：1. 北京理工大学光电学院, 北京 100081;
2. 北京理工大学长三角研究院(嘉兴), 浙江 嘉兴 314003
关键词：时间数字转换器;fpga;延时链;相控时钟
摘要：
高精度时间间隔测量过程中，为兼顾测量分辨和精度的同时，简化校准过程，提出一种混合架构的时间数字转换器(tdc)设计方法。该方法将相控时钟架构与抽头延时链（tdl）架构结合，利用不同相位的时钟对抽头延时链实现并行采样，一次测量过程中可以得到多个测量值，最后利用多个测量值的均值表示测量结果。该方法在kintex-7 fpga上进行实验测试，结果表明在进行简单校准的情况下，仍然可以保持较高的测量分辨率和精度，从而证明提出方法的有效性与可行性。
hybrid architecture time to digital converter with phased clocks-delay chains
li guoliang1, han bin1, cheng yang1,2, cao jie1,2, bao chun1, wu haoze1
1. school of optics and photonics, beijing institute of technology, beijing 100081, china;
2. yangtze delta region academy of beijing institute of technology, jiaxing 314003, china
abstract: in the process of high precision time interval measurement, in order to simplify the calibration process without affecting the measurement resolution and accuracy, a hybrid architecture time to digital converter (tdc) design method is proposed. this method combines the phased clock architecture with the tap delay line (tdl) architecture, and the clock with different phases is used to sample the tap delay line in parallel. multiple measured values can be obtained in a single measurement process, and the mean value of multiple measured values is used to represent the measurement results. the presented method is implemented on a kintex-7 fpga, and the results show that the proposed method can still maintain high measurement resolution and accuracy even with simple calibration, which proves the effectiveness and feasibility of the proposed method.
keywords: time to digital converter;field programmable gate array;delay chains;phased clocks
2023, 49(6):130-136 收稿日期: 2022-01-08;收到修改稿日期: 2022-03-25
基金项目: 北京市自然科学基金（4222017）
作者简介: 李国梁(1996-),男,山西忻州市人,硕士研究生,专业方向为高精度时间测量
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